About the Role
Urgently looking for an experienced Design Verification Engineer to work from office in Cambridge, UK. Design Verification Engineer must have a minimum of 8+ years of relevant experience & Strong verification experience with knowledge of SystemVerilog, UVM.
Requirements
Strong verification experience with knowledge of SystemVerilog, UVM
System verification (C based) experience is a must.
Good knowledge of testplan creation and tracking.
Low-level programming experience including C and Assembler.
Experience with full verification flow including coverage closure.
Experience with ARM-based designs and/or ARM System Architectures
AXI, CHI protocol knowledge.
About the Company
Our client is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions.
It offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide. It provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. It offers a Turnkey ASIC Solution, from design to packaged parts. They have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.
It offers a highly competitive compensation and benefits along with an electric work environment to scale one’s intellect, skills and growth.